The present invention relates to a technology for designing a lower-power integrated circuit.
Recently, power reduction in a data processing system has become an issue of great importance. In mobile equipment that has rapidly become prevalent in recent years, the lifetime of a battery may have a direct influence on the value of a product so that it is important to reduce energy consumption and increase the lifetime of the battery. In a stationary system also, the trend has been energy saving for cost reductions in the package and cooling device thereof.
Examples of currently-known power management mechanisms for achieving lower power consumption include a mechanism for cutting off a power supply or a clock supply to a circuit block which is not used and a mechanism for directing, during the standby of a system, a circuit block to use a power-supply voltage and an operating frequency each lower than during the operation of the system.
If a system is constructed by combining a plurality of blocks having such a power control mechanism, power management of the system should be performed to determine a time at which a power supply to a certain block is halted, a time at which a power-supply voltage supplied to a certain block is changed, and an amount of change in power-supply voltage.
The followings are known examples of conventional power management technologies.
Japanese Laid-Open Patent Publication No. 7-44286 discloses a power management method for a computer system, in which a power supply to each of peripheral circuits (slaves) connected to a CPU (master) is controlled by using the plurality of operating states of the system. In accordance with the method, each of the peripheral circuits is switched between a high-power operating state using a high power-supply voltage and a low-power operating state using a low power-supply voltage depending on the state of the system. As the states of the system, there are a normal operating state, a standby state, and a suspended state. Since the CPU is capable of determining the state of the system and properly switching the operating state of the peripheral circuit, power consumption can be reduced.
On the other hand, Japanese Laid-Open Patent Publication No. 2000-102080 discloses a power management system for electric devices, in which a plurality of electric devices transmit data for power management therebetween via a common network cable such that power management is performed. Each of the electric devices periodically outputs a code indicative of the On/Off state of the electric device to the network cable. The electric device predetermined to operate as the master interprets the code and effects On/Off control over the other electric devices operating as the slaves.
Thus, in each of the conventional technologies, one predetermined master gives an instruction to a power control mechanism for each of the slaves as a target for power control and controls power consumption in the slave, thereby performing power management of the entire system. In other words, the master performs centralized management of power control.
In each of the conventional power management methods, the master explicitly transmits a control signal to the power control mechanism for the slaves. Accordingly, the master should be designed in compliance with the power control mechanism for the slaves. Conversely, the slaves should also be designed in accordance with the control method of the master.
In recent design of an integrated circuit, block-based design using, e.g., IP (intellectual property), macro, VC (virtual component), or the like has been the main stream to achieve a reduced design period. If an integrated circuit system is constructed by combining a plurality of existing design blocks, however, the blocks should be re-designed such that power management is performed. This leads to the problem of a larger number of design steps.
If a certain existing design block is to be incorporated as a master into a system, to control a clock supply to a block operating as a slave, the block serving as the master should be re-designed to transmit to each of the blocks a signal for controlling the block.